Module 1
Process steps in 1C fabrication: Crystal growth and wafer preparation- Czochralski process- apparatus- silicon shaping, slicing and polishing- Diffusion of impurities-physical mechanism- Pick’s I and II law of diffusion- Diffusion profiles- complementary (erfc) error function- Gaussian profile- Ion implantation- Annealing process- Oxidation process- Lithography- Photolithography, Fine line lithography, electron beam and x-ray lithography- Chemical vapour deposition (CVD)- epitaxial growth- reactors-metallisation- patterning- wire bonding and packaging.
Process steps in 1C fabrication: Crystal growth and wafer preparation- Czochralski process- apparatus- silicon shaping, slicing and polishing- Diffusion of impurities-physical mechanism- Pick’s I and II law of diffusion- Diffusion profiles- complementary (erfc) error function- Gaussian profile- Ion implantation- Annealing process- Oxidation process- Lithography- Photolithography, Fine line lithography, electron beam and x-ray lithography- Chemical vapour deposition (CVD)- epitaxial growth- reactors-metallisation- patterning- wire bonding and packaging.
Module 2
Monolithic components: Isolation of components- junction isolation and dielectric isolation- Transistor fabrication- buried layer- impurity profile- parasitic effects-monolithic diodes- schottky diodes and transistors- FET structures- JFET- MOSFET-PMOS and NMOS, control of threshold voltage (Vth)- silicon gate technology-Monolithic resistors- sheet resistance and resistor design- resistors in diffused regions-MOS resistors- monolithic capacitors- junction and MOS structures- 1C crossovers and vias.
Monolithic components: Isolation of components- junction isolation and dielectric isolation- Transistor fabrication- buried layer- impurity profile- parasitic effects-monolithic diodes- schottky diodes and transistors- FET structures- JFET- MOSFET-PMOS and NMOS, control of threshold voltage (Vth)- silicon gate technology-Monolithic resistors- sheet resistance and resistor design- resistors in diffused regions-MOS resistors- monolithic capacitors- junction and MOS structures- 1C crossovers and vias.
Module 3
CMOS technology: Metal gate and silicon gate- oxide isolation- Twin well process- Latch up- BiCMOS technology- fabrication steps- circuit design process- stick diagrams- design rules- Capacitance of layers- Delay- Driving large capacitance loads- Wiring capacitance- Basic circuit concepts- scaling of MOS structures- scaling factors- effects of miniaturization.
CMOS technology: Metal gate and silicon gate- oxide isolation- Twin well process- Latch up- BiCMOS technology- fabrication steps- circuit design process- stick diagrams- design rules- Capacitance of layers- Delay- Driving large capacitance loads- Wiring capacitance- Basic circuit concepts- scaling of MOS structures- scaling factors- effects of miniaturization.
Module 4
Subsystem design and layout- Simple logic circuits- inverter, NAND gates, BiCMOS circuit, NOR gates, CMOS logic systems – bus lines- arrangements- power dissipation-power supply rail distribution- subsystem design process- design of a 4 bit shifter.
Subsystem design and layout- Simple logic circuits- inverter, NAND gates, BiCMOS circuit, NOR gates, CMOS logic systems – bus lines- arrangements- power dissipation-power supply rail distribution- subsystem design process- design of a 4 bit shifter.
Module 5
Gallium Arsenide Technology: Sub-micro CMOS technology- Crystal structure- Doping process- Channeling effect- MESFET- GaAs fabrication- Device modeling.
Gallium Arsenide Technology: Sub-micro CMOS technology- Crystal structure- Doping process- Channeling effect- MESFET- GaAs fabrication- Device modeling.
References
VLSI technology. S M Sze, Me Graw Hill pub,
Basic VLSI design: Douglas Pucknell, PHI
Principles of CMOS VLSI Design: H E Weste, Pearson Edn.
4. Integrated Circuits: K R Botkar, Khanna Pub.
CMOS circuit design layout and simulation: Barter, IEEE press.
Introduction to VLSI: Conway, Addison weslay.
Basic VLSI design: Douglas Pucknell, PHI
Principles of CMOS VLSI Design: H E Weste, Pearson Edn.
4. Integrated Circuits: K R Botkar, Khanna Pub.
CMOS circuit design layout and simulation: Barter, IEEE press.
Introduction to VLSI: Conway, Addison weslay.