Module 1
Introduction Hardware Abstraction- Basic Terminology- Entity Declaration- Architecture Body- Configuration Declaration- Package Declaration- Package Body- Model Analysis- Simulation- Basic Language Elements –Identifiers- Data Objects- Data Types- Operators.
Introduction Hardware Abstraction- Basic Terminology- Entity Declaration- Architecture Body- Configuration Declaration- Package Declaration- Package Body- Model Analysis- Simulation- Basic Language Elements –Identifiers- Data Objects- Data Types- Operators.
Module 2
Behavioural Modelling Entity Declaration- Architecture Body-Process Statement- Variable Assignment Statement- Signal Assignment Statement- Wait Statement- If Statement – Case Statement- Null Statement- Loop Statement- Exit Statement- Next Statement- Assertion Statement- Report Statement- Other Sequential Statements- Multiple Processes- Postponed Processes – Dataflow Modelling Concurrent Signal Assignment Statement- Concurrent versus Sequential Signal Assignment- Delta Delay Revisited- Multiple Drivers- Conditional Signal Assignment Statement- Selected Signal Assignment Statement- the UNAFFECTED Value- Block Statement- Concurrent Assertion Statement- Value of a Signal
Behavioural Modelling Entity Declaration- Architecture Body-Process Statement- Variable Assignment Statement- Signal Assignment Statement- Wait Statement- If Statement – Case Statement- Null Statement- Loop Statement- Exit Statement- Next Statement- Assertion Statement- Report Statement- Other Sequential Statements- Multiple Processes- Postponed Processes – Dataflow Modelling Concurrent Signal Assignment Statement- Concurrent versus Sequential Signal Assignment- Delta Delay Revisited- Multiple Drivers- Conditional Signal Assignment Statement- Selected Signal Assignment Statement- the UNAFFECTED Value- Block Statement- Concurrent Assertion Statement- Value of a Signal
Module 3
Structural Modelling Component Declaration- Component Instantiation- Resolving Signal Values – Generics and Configurations Generics- Configurations- Configuration Specification- Configuration Declaration- Default Rules – Conversion Functions – Direct Instantiation- Incremental Binding.
Structural Modelling Component Declaration- Component Instantiation- Resolving Signal Values – Generics and Configurations Generics- Configurations- Configuration Specification- Configuration Declaration- Default Rules – Conversion Functions – Direct Instantiation- Incremental Binding.
Module 4
Subprograms and Overloading Subprograms- Subprogram Overloading- Operator Overloading- Signatures- Default Values for Parameters – Packages and Libraries Package Declaration- Package Body-Design File- Design Libraries-Order of Analysis- Implicit Visibility- Explicit Visibility.
Subprograms and Overloading Subprograms- Subprogram Overloading- Operator Overloading- Signatures- Default Values for Parameters – Packages and Libraries Package Declaration- Package Body-Design File- Design Libraries-Order of Analysis- Implicit Visibility- Explicit Visibility.
Module 5
Advanced Features Entity Statements- Generate Statements- Aliases- Qualified Expressions- Type Conversions- Guarded Signals- Attributes- Aggregate Targets- Shared Variables- Groups – Model Simulation Simulation- Writing a Test Bench- Converting Real and Integer to Time- Dumping Results into a Text Fi1e- Reading Vectors from a Text File- A Test Bench Example- Initialising a Memory- Variable File Names- Hardware Modelling Examples Modelling Entity interfaces- Modelling Simple Elements- – Different Styles of Modelling- Modelling Regular Structures- Modelling Delays- Modelling Conditional Operations- Modelling Synchronous Logic- State Machine Modelling- Interacting State Machines- Modelling a Moore FSM- Modelling a Mealy FSM- A Generic Priority Encoder- A Simplified Blackjack Program- A Clock Divider- A Generic Binary Multiplier- A Pulse Counter- A Barrel Shifter- Hierarchy in Design.
Advanced Features Entity Statements- Generate Statements- Aliases- Qualified Expressions- Type Conversions- Guarded Signals- Attributes- Aggregate Targets- Shared Variables- Groups – Model Simulation Simulation- Writing a Test Bench- Converting Real and Integer to Time- Dumping Results into a Text Fi1e- Reading Vectors from a Text File- A Test Bench Example- Initialising a Memory- Variable File Names- Hardware Modelling Examples Modelling Entity interfaces- Modelling Simple Elements- – Different Styles of Modelling- Modelling Regular Structures- Modelling Delays- Modelling Conditional Operations- Modelling Synchronous Logic- State Machine Modelling- Interacting State Machines- Modelling a Moore FSM- Modelling a Mealy FSM- A Generic Priority Encoder- A Simplified Blackjack Program- A Clock Divider- A Generic Binary Multiplier- A Pulse Counter- A Barrel Shifter- Hierarchy in Design.
Text Book
VHDL Primer Third editions J. Bhasker, Pearson Education Asia.
mgu university b.tech syllabus electronics
References
References
1. Introducing VHDL from simulation to synthesis Sudhakar Yalamanchilli, Pearson Education Asia